{
  "schema": "lri.research-domain-workbench/v1",
  "topic": {
    "id": "huawei_tau_scaling",
    "title": "华为韬(τ)定律",
    "title_en": "Huawei Tau (τ) Scaling Law",
    "subtitle": "从几何缩微转向跨层时间缩微的候选工程框架",
    "goal": "建立可证伪、可对照、可持续刷新的韬定律研究专题，区分厂商主张、会议事实、独立评价与待验证路线图。",
    "canonical_entry": "workbench.html",
    "status": "evidence_bounded_seed",
    "last_verified": "2026-07-17"
  },
  "scope": {
    "include": [
      "τ Scaling 的定义与指标",
      "LogicFolding",
      "器件/电路/芯片/系统协同",
      "麒麟与 AI 计算实践",
      "与 Moore/Dennard/3D 集成/PPA 的关系"
    ],
    "exclude": [
      "未经证据的制程能力推断",
      "把等效密度写成真实工艺节点",
      "把厂商自述写成同行评审结论"
    ]
  },
  "thesis": [
    {
      "id": "k1",
      "grade": "L2",
      "claim": "韬(τ)定律当前应被视为华为提出的跨层缩时工程框架，而不是已经获得行业共识的物理或经验定律。",
      "evidence_refs": [
        "c1",
        "c3",
        "c7"
      ],
      "decision_use": "决定专题措辞和后续证据优先级。"
    },
    {
      "id": "k2",
      "grade": "L1",
      "claim": "公开材料中最可检验的技术抓手是 LogicFolding，但尚缺结构、PPA 和对照基线，无法判断独立新颖性与收益来源。",
      "evidence_refs": [
        "c2",
        "v2",
        "v3"
      ],
      "decision_use": "把版图/PPA/独立测试列为 P0。"
    },
    {
      "id": "k3",
      "grade": "L2",
      "claim": "τ Scaling 的重要价值可能不是单项技术，而是把器件 RC、关键路径、任务执行时间和系统通信时延统一到 time-to-solution 目标。",
      "evidence_refs": [
        "c3",
        "v1",
        "v4",
        "v5"
      ],
      "decision_use": "建立跨层指标矩阵，但不假定存在单一公式。"
    },
    {
      "id": "k4",
      "grade": "Boundary",
      "claim": "381 款芯片、秋季麒麟性能提升和 2031 年 1.4nm 等效密度均需独立产品、测量和定义证据才能升级。",
      "evidence_refs": [
        "c4",
        "c5",
        "c6"
      ],
      "decision_use": "阻止路线图和厂商自述被误写成已验证结果。"
    }
  ],
  "tracks": [
    {
      "id": "formalism",
      "name": "统一指标与可证伪性",
      "description": "研究 τ 的定义、跨层聚合方式、边界条件和与 Moore/Dennard/PPA/time-to-solution 的关系。"
    },
    {
      "id": "device_circuit",
      "name": "器件、互连与 LogicFolding",
      "description": "分析 RC、关键路径、布局布线、3D/先进封装及逻辑折叠的真实技术边界。"
    },
    {
      "id": "chip_stack",
      "name": "软件—架构—芯片协同",
      "description": "验证 workload 驱动的指令流/数据流控制是否产生端到端性能和能效收益。"
    },
    {
      "id": "system",
      "name": "系统互联与超节点",
      "description": "研究统一编址、原生内存语义、通信时延、扩展性和一致性成本。"
    },
    {
      "id": "industrial",
      "name": "产品与产业验证",
      "description": "跟踪 2026 麒麟、AI 计算产品、第三方评测、论文、专利和量产证据。"
    }
  ],
  "overview_map": [
    {
      "layer": "L1",
      "title": "问题",
      "description": "几何缩微放缓和成本红利下降后，如何继续提升性能、能效与密度。"
    },
    {
      "layer": "L2",
      "title": "原则",
      "description": "把优化主轴从空间尺寸转向器件、电路、芯片和系统的时间量。"
    },
    {
      "layer": "L3",
      "title": "实现",
      "description": "LogicFolding、全栈软硬芯协同和系统互联重构。"
    },
    {
      "layer": "L4",
      "title": "验证",
      "description": "用统一基线测量 PPA、端到端时延、能耗、密度和扩展成本。"
    },
    {
      "layer": "L5",
      "title": "产业证据",
      "description": "产品、论文、专利、独立测试和第三方复现决定是否升级。"
    }
  ],
  "capability_matrix": [
    {
      "capability": "Formal tau model",
      "track": "formalism",
      "primary_resources": [
        "src_ieee_keynote",
        "src_huawei_cn"
      ],
      "gap": "没有公开统一公式、聚合方法和适用边界。"
    },
    {
      "capability": "LogicFolding circuit evidence",
      "track": "device_circuit",
      "primary_resources": [
        "src_huawei_cn"
      ],
      "gap": "缺版图、结构、PPA 和同工艺基线。"
    },
    {
      "capability": "Workload-aware co-design",
      "track": "chip_stack",
      "primary_resources": [
        "src_huawei_cn",
        "src_ieee_forum"
      ],
      "gap": "缺公开 workload 与端到端测量。"
    },
    {
      "capability": "Unified system interconnect",
      "track": "system",
      "primary_resources": [
        "src_huawei_cn"
      ],
      "gap": "缺协议、规模、延迟和一致性数据。"
    },
    {
      "capability": "Independent industrial validation",
      "track": "industrial",
      "primary_resources": [
        "src_reuters_huawei",
        "src_reuters_tsmc"
      ],
      "gap": "缺公开产品、论文与第三方复现。"
    }
  ],
  "claims": [
    {
      "id": "c1",
      "statement": "华为在 IEEE ISCAS 2026 主旨演讲中提出以时间常数/端到端时间缩微为核心的 τ Scaling 原则。",
      "grade": "Direct",
      "status": "supported",
      "evidence_refs": [
        "src_huawei_cn",
        "src_ieee_keynote",
        "src_ieee_program"
      ],
      "allowed_wording": "华为提出的后摩尔时代工程原则",
      "forbidden_wording": "已被 IEEE 或产业界确立的新定律"
    },
    {
      "id": "c2",
      "statement": "LogicFolding 被华为描述为缩短关键路径走线、降低 RC 负载并同时改善密度和性能的电路层实现。",
      "grade": "L1 self-reported",
      "status": "needs_public_design_evidence",
      "evidence_refs": [
        "src_huawei_cn"
      ],
      "allowed_wording": "华为公布的核心实现方向",
      "forbidden_wording": "已公开复现的通用逻辑折叠技术"
    },
    {
      "id": "c3",
      "statement": "τ Scaling 的范围覆盖器件、电路、芯片和系统四层，并以缩短不同层级的时间量为共同目标。",
      "grade": "Direct framework claim",
      "status": "supported_as_framework",
      "evidence_refs": [
        "src_huawei_cn",
        "src_ieee_keynote",
        "src_ieee_forum"
      ],
      "allowed_wording": "多层协同框架",
      "forbidden_wording": "已经具有统一数学定义的跨层定律"
    },
    {
      "id": "c4",
      "statement": "华为称过去六年基于该原则设计并量产 381 款芯片。",
      "grade": "Self-reported with discrepancy",
      "status": "blocked_for_upgrade",
      "evidence_refs": [
        "src_huawei_cn",
        "src_ieee_keynote"
      ],
      "allowed_wording": "华为新闻稿称 381 款；IEEE 摘要另称五年 150+ advanced chips",
      "forbidden_wording": "已独立核验的 381 款量产芯片"
    },
    {
      "id": "c5",
      "statement": "华为称 2026 年秋季麒麟芯片将首次采用 LogicFolding，并显著提升性能。",
      "grade": "Future vendor claim",
      "status": "future_validation",
      "evidence_refs": [
        "src_huawei_cn"
      ],
      "allowed_wording": "待产品发布和独立测试验证的路线图",
      "forbidden_wording": "LogicFolding 已在公开麒麟产品中验证"
    },
    {
      "id": "c6",
      "statement": "华为预计 2031 年高端芯片可达到 1.4nm 制程同等晶体管密度。",
      "grade": "Long-range forecast",
      "status": "definition_blocked",
      "evidence_refs": [
        "src_huawei_cn",
        "src_reuters_huawei"
      ],
      "allowed_wording": "华为的等效密度目标",
      "forbidden_wording": "将制造真正的 1.4nm 工艺芯片"
    },
    {
      "id": "c7",
      "statement": "τ Scaling 是否构成超越现有 3D 集成、先进封装、PPA 优化和全栈协同的独立新定律，目前没有足够公开证据。",
      "grade": "L2 bounded inference",
      "status": "open_research_question",
      "evidence_refs": [
        "src_ieee_forum",
        "src_reuters_huawei",
        "src_reuters_tsmc"
      ],
      "allowed_wording": "候选统一工程框架，其独立新颖性和普适性待验证",
      "forbidden_wording": "τ Scaling 只是宣传或已取代摩尔定律"
    }
  ],
  "verification_gates": [
    {
      "id": "v1",
      "name": "Formal definition",
      "question": "τ 在四层分别如何定义、归一和聚合？",
      "minimum_evidence": "公开公式、变量定义、适用范围和反例。",
      "upgrade": "从叙事框架升级为可检验理论。"
    },
    {
      "id": "v2",
      "name": "LogicFolding implementation",
      "question": "逻辑折叠是 3D/2.5D 集成、布局布线、单元架构还是组合方法？",
      "minimum_evidence": "版图/截面、关键路径、面积、频率、功耗与工艺基线。",
      "upgrade": "从厂商术语升级为可比较电路技术。"
    },
    {
      "id": "v3",
      "name": "Chip PPA comparison",
      "question": "在同工艺、同面积或同功耗约束下收益多大？",
      "minimum_evidence": "至少两个基线、工作负载、PPA 表和误差/条件。",
      "upgrade": "证明收益不是由不同工艺或规模造成。"
    },
    {
      "id": "v4",
      "name": "End-to-end workload",
      "question": "软件—架构—芯片协同是否降低真实任务时间和能耗？",
      "minimum_evidence": "端到端 workload、延迟、吞吐、能耗和质量约束。",
      "upgrade": "从局部时延优化升级为系统效益。"
    },
    {
      "id": "v5",
      "name": "System interconnect",
      "question": "灵衢/统一内存语义的延迟、带宽、一致性和扩展代价如何？",
      "minimum_evidence": "拓扑、协议、规模曲线、失败恢复和对照系统。",
      "upgrade": "验证系统层 τ 缩微。"
    },
    {
      "id": "v6",
      "name": "Independent reproduction",
      "question": "第三方能否复现或审查关键结论？",
      "minimum_evidence": "同行评审论文、开源/专利细节、独立测量或产品拆解。",
      "upgrade": "从单一厂商证据升级为外部可信证据。"
    }
  ],
  "evidence_sources": [
    {
      "id": "src_huawei_cn",
      "title": "华为发表韬(τ)定律，实现晶体管密度与系统性能突破",
      "publisher": "Huawei",
      "url": "https://www.huawei.com/cn/news/2026/5/ieee-iscas-tau-scaling",
      "source_type": "official_announcement",
      "grade": "Direct for Huawei statements",
      "supports": [
        "c1",
        "c2",
        "c3",
        "c4",
        "c5",
        "c6"
      ],
      "boundary": "证明华为公开提出与自述的工程实践，不等于第三方验证或同行评审。"
    },
    {
      "id": "src_huawei_en",
      "title": "HUAWEI Presents the Tau (τ) Scaling Law",
      "publisher": "Huawei",
      "url": "https://www.huawei.com/en/news/2026/5/ieee-iscas-tau-scaling",
      "source_type": "official_announcement",
      "grade": "Direct duplicate-language source",
      "supports": [
        "c1",
        "c2",
        "c3",
        "c4",
        "c5",
        "c6"
      ],
      "boundary": "英文版用于术语对照，不计作独立证据。"
    },
    {
      "id": "src_ieee_keynote",
      "title": "IEEE ISCAS 2026 Keynote: New Semiconductor Path in Practice",
      "publisher": "IEEE ISCAS 2026",
      "url": "https://2026.ieee-iscas.org/program/keynote.html",
      "source_type": "conference_primary",
      "grade": "Direct event and abstract evidence",
      "supports": [
        "c1",
        "c3",
        "c4_discrepancy"
      ],
      "boundary": "确认演讲身份、题目与摘要；页面未公开完整 τ 定律公式和实验数据。"
    },
    {
      "id": "src_ieee_program",
      "title": "IEEE ISCAS 2026 Program at a Glance",
      "publisher": "IEEE ISCAS 2026",
      "url": "https://2026.ieee-iscas.org/program/Program-At-a-Glance.html",
      "source_type": "conference_primary",
      "grade": "Direct schedule evidence",
      "supports": [
        "c1"
      ],
      "boundary": "只证明主旨演讲被安排在会议日程。"
    },
    {
      "id": "src_ieee_forum",
      "title": "IEEE ISCAS 2026 Industry Forum II: Charting the Next Era of Semiconductors",
      "publisher": "IEEE ISCAS 2026",
      "url": "https://2026.ieee-iscas.org/program/Industry-Forum-II.html",
      "source_type": "conference_primary_context",
      "grade": "Direct context evidence",
      "supports": [
        "c3",
        "c7"
      ],
      "boundary": "证明后摩尔时代问题与架构实践是会议议题，不证明华为方案优越。"
    },
    {
      "id": "src_reuters_huawei",
      "title": "Huawei looks beyond Moore's Law",
      "publisher": "Reuters",
      "url": "https://www.reuters.com/technology/artificial-intelligence/huawei-looks-beyond-moores-law-2026-05-27/",
      "source_type": "independent_secondary",
      "grade": "Independent secondary assessment",
      "supports": [
        "c7",
        "c6_boundary"
      ],
      "boundary": "可用于行业质疑与背景，不替代技术论文和测量数据。"
    },
    {
      "id": "src_reuters_tsmc",
      "title": "Energy use forcing rethink of AI chip design, TSMC says",
      "publisher": "Reuters",
      "url": "https://www.reuters.com/business/retail-consumer/energy-use-forcing-rethink-ai-chip-design-tsmc-says-2026-05-28/",
      "source_type": "independent_secondary_counterview",
      "grade": "Independent counterview",
      "supports": [
        "c7"
      ],
      "boundary": "说明缩短数据移动、3D 堆叠和能效优化并非只有一个产业路径。"
    }
  ],
  "evidence_gaps": [
    {
      "gap": "未找到公开的 τ Scaling 同行评审论文或完整主旨演讲材料",
      "severity": "P0",
      "next_action": "跟踪 IEEE Xplore、ISCAS proceedings、华为论文/专利和演讲视频。"
    },
    {
      "gap": "LogicFolding 缺少公开结构和 PPA 对照",
      "severity": "P0",
      "next_action": "收集专利、版图示意、产品拆解与同工艺基准。"
    },
    {
      "gap": "381 与 150+ 芯片口径不一致",
      "severity": "P0",
      "next_action": "明确时间窗、advanced/design/mass-produced 的统计口径。"
    },
    {
      "gap": "1.4nm 等效密度缺少等效定义",
      "severity": "P0",
      "next_action": "要求 transistor/mm²、SRAM/logic mix、面积和工艺基线。"
    },
    {
      "gap": "系统层灵衢收益缺公开规模曲线",
      "severity": "P1",
      "next_action": "补协议、拓扑、带宽/时延/一致性与超节点对照。"
    }
  ],
  "risks": [
    {
      "risk": "品牌化命名被误当成自然定律",
      "impact": "混淆厂商方法、经验规律与行业共识。",
      "mitigation": "所有页面固定显示 Proposed framework / 待独立验证。"
    },
    {
      "risk": "跨层指标不可比",
      "impact": "局部 RC、芯片任务时间和系统通信时延被错误相加。",
      "mitigation": "每层独立定义 τ，只有在明确聚合模型后才能跨层综合。"
    },
    {
      "risk": "等效节点营销化",
      "impact": "把密度、性能或系统收益误写成真实制程。",
      "mitigation": "强制记录等效维度、基线和不等价项。"
    },
    {
      "risk": "选择性基线",
      "impact": "不同工艺、面积、功耗或 workload 造成虚假收益。",
      "mitigation": "使用同约束对照和完整 PPA/time-to-solution 表。"
    }
  ],
  "resource_profiles": [
    {
      "name": "Huawei official τ Scaling announcement",
      "type": "official claim source",
      "status": "indexed",
      "description": "器件—系统四层框架、LogicFolding、381 芯片与路线图的原始厂商表述。"
    },
    {
      "name": "IEEE ISCAS keynote page",
      "type": "conference primary source",
      "status": "indexed",
      "description": "确认演讲、摘要和后摩尔时代问题定义。"
    },
    {
      "name": "IEEE ISCAS Industry Forum II",
      "type": "industry context",
      "status": "indexed",
      "description": "提供架构创新与工程权衡的会议语境。"
    },
    {
      "name": "Future peer-reviewed paper/patent set",
      "type": "missing primary technical evidence",
      "status": "P0 backlog",
      "description": "需要公开公式、结构、实验与适用边界。"
    },
    {
      "name": "Kirin 2026 independent benchmark/teardown",
      "type": "future validation asset",
      "status": "watch",
      "description": "验证 LogicFolding 是否落地及真实 PPA/性能收益。"
    }
  ],
  "next_steps": [
    {
      "title": "恢复完整技术材料",
      "description": "检索 ISCAS proceedings、IEEE Xplore、演讲视频、华为论文和专利。"
    },
    {
      "title": "建立对照矩阵",
      "description": "与 Moore/Dennard、3D IC、先进封装、chiplet、PPA 和 time-to-solution 对照。"
    },
    {
      "title": "跟踪麒麟产品证据",
      "description": "记录产品规格、面积、功耗、频率、性能和第三方拆解。"
    },
    {
      "title": "验证系统层",
      "description": "收集灵衢/超节点的协议、规模曲线和通信时延。"
    },
    {
      "title": "季度刷新",
      "description": "任何 Claim 升级必须绑定新增公开证据和 Validator。"
    }
  ],
  "review_methodology_status": {
    "review_type": "rapid evidence-bounded domain review",
    "protocol": "sources/search_protocol.yaml",
    "search_log": "sources/search_log.csv",
    "screening_log": "sources/screening_log.csv",
    "quality_matrix": "sources/evidence_quality_matrix.json",
    "traceability": "data/claim_traceability_matrix.json"
  }
}